Benoit Dupont De Dinechin

ScholarGPS® ID: 42514387527480

Affiliation

Intel Corporation, Santa Clara, United States

Affiliation History

Field

Engineering and Computer Science

Discipline

Electrical and Computer Engineering

Top Specialties

Metrics Summary

Publication Count

Predicted Citations

1,063

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Ranking

Publications and Citation History

Publications based on Top Specialties

Types of Publication

Publications
Books
Patents
NIH/NSF

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Distortion Approximation of a Compressed Softmax Layer (conference) Resmerita, Diana \| Farias, Rodrigo Cabral \| de Dinechin, Benoit Dupont \| Fillatre, Lionel 2021 IEEE Statistical Signal Processing Workshop (SSP) (2021) Rio de Janeiro, Brazil 10.1109/SSP49050.2021.9513733 Cited by (1) \| Cite \| Source
A study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory (conference) Schuh, Matheus \| Maiza, Claire \| Goossens, Joel \| Raymond, Pascal \| de Dinechin, Benoit Dupont 2020 IEEE Real-Time Systems Symposium (RTSS) (2020) Houston, TX, USA 10.1109/RTSS49844.2020.00034 Cited by (5) \| Cite \| Source
Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip (conference) Graillat, Amaury \| Maiza, Claire \| Moy, Matthieu \| Raymond, Pascal \| de Dinechin, Benoît Dupont RTNS 2019: 27th International Conference on Real-Time Networks and Systems (2019) Toulouse France 10.1145/3356401.3356416 Cited by (2) \| Cite \| Source
Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor (conference) de Dinechin, Benoît Dupont DAC '19: The 56th Annual Design Automation Conference 2019 (2019) Las Vegas NV USA 10.1145/3316781.3323473 Cited by (6) \| Cite \| Source
Co-Design and Abstraction of a Network-on-Chip Using Deterministic Network Calculus (conference) de Dinechin, Benoît Dupont 2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS) (2018) Turin, Italy 10.1109/NOCS.2018.8512177 Cite \| Source
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore (conference) Hascoe, Julien \| de Dinechin, Benoet Dupont \| Desnos, Karol \| Nezan, Jean-Francois 2018 IEEE High Performance Extreme Computing Conference (HPEC) (2018) Waltham, MA 10.1109/HPEC.2018.8547736 Cited by (4) \| Cite \| Source
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems (journal article) Giannopoulou, Georgia \| Poplavko, Peter \| Socci, Dario \| Huang, Pengcheng \| Stoimenov, Nikolay \| Bourgos, Paraskevas \| Thiele, Lothar \| Bozga, Marius \| Bensalem, Saddek \| Girbal, Sylvain \| ... \| de Dinechin, Benoît Dupont Design Automation for Embedded Systems, volume 22, issue 1-2, pages 141-181 (2018). 10.1007/s10617-018-9206-3 Cited by (3) \| Cite \| Source
Parallel code generation of synchronous programs for a many-core architecture (conference) Graillat, Amaury \| Moy, Matthieu \| Raymond, Pascal \| de Dinechin, Benoit Dupont 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2018) Dresden, Germany 10.23919/DATE.2018.8342182 Cited by (10) \| Cite \| Source \| Open Access
Improving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors (conference) Ho, Minh Quan \| Obrecht, Christian \| Tourancheau, Bernard \| de Dinechin, Benoit Dupont \| Hascoet, Julien 2017 IEEE 36th International Performance Computing and Communications Conference (IPCCC) (2017) San Diego, CA 10.1109/PCCC.2017.8280472 Cited by (6) \| Cite \| Source \| Open Access
Asynchronous one-sided communications and synchronizations for a clustered manycore processor (conference) Hascoët, Julien \| de Dinechin, Benoît Dupont \| de Massas, Pierre Guironnet \| Ho, Minh Quan ESWEEK'17: THIRTEENTH EMBEDDED SYSTEM WEEK (2017) Seoul Republic of Korea 10.1145/3139315.3139318 Cited by (9) \| Cite \| Source
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor (conference) de Dinechin, Benoît Dupont \| Graillat, Amaury MICRO-50: The 50th Annual IEEE/ACM International Symposium on Microarchitecture (2017) Cambridge MA USA 10.1145/3139540.3139542 Cited by (2) \| Cite \| Source
Hierarchical Dataflow Model for efficient programming of clustered manycore processors (conference) Hascoet, Julien \| Desnos, Karol \| Nezan, Jean-Francois \| de Dinechin, Benoit Dupont 2017 IEEE 28th International Conference on Application-specific Systems, Architectures and Processors (ASAP) (2017) Seattle, WA, USA 10.1109/ASAP.2017.7995270 Cited by (11) \| Cite \| Source \| Open Access
Network-on-chip service guarantees on the kalray MPPA-256 bostan processor (conference) de Dinechin, Benoît Dupont \| Graillat, Amaury AISTECS '17: 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (2017) Stockholm Sweden 10.1145/3073763.3073770 Cited by (11) \| Cite \| Source
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources (journal article) Giannopoulou, Georgia \| Stoimenov, Nikolay \| Huang, Pengcheng \| Thiele, Lothar \| de Dinechin, Benoît Dupont Real-Time Systems, volume 52, issue 4, pages 399-449 (2016). 10.1007/s11241-015-9227-y Cited by (47) \| Cite \| Source
Optimal and fast throughput evaluation of CSDF (conference) Bodin, Bruno \| Munier-Kordon, Alix \| de Dinechin, Benoît Dupont DAC '16: The 53rd Annual Design Automation Conference 2016 (2016) Austin Texas 10.1145/2897937.2898056 Cited by (12) \| Cite \| Source \| Open Access
The shift to multicores in real-time and safety-critical systems (conference) Saidi, Selma \| Ernst, Rolf \| Uhrig, Sascha \| Theiling, Henrik \| de Dinechin, Benoit Dupont 2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (2015) Amsterdam, Netherlands 10.1109/CODESISSS.2015.7331385 Cited by (49) \| Cite \| Source
Implementation of a Fast Fourier transform algorithm onto a manycore processor (conference) Hascoet, Julien \| Nezan, Jean-Francois \| Ensor, Andrew \| de Dinechin, Benoit Dupont 2015 Conference on Design and Architectures for Signal and Image Processing (DASIP) (2015) Krakow, Poland 10.1109/DASIP.2015.7367270 Cited by (8) \| Cite \| Source \| Open Access
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor (conference) de Dinechin, Benoit Dupont 2015 IEEE Hot Chips 27 Symposium (HCS) (2015) Cupertino, CA, USA 10.1109/HOTCHIPS.2015.7477332 Cited by (17) \| Cite \| Source
Bit-matrix multiplication using explicit register (patent) Dinechin, Benoît Dupont de \| Rybczynska, Marta Patent Number: 20150339101 (2015) Cite \| Source
Guaranteed Services of the NoC of a Manycore Processor (conference) de Dinechin, Benoît Dupont \| Durand, Yves \| van Amstel, Duco \| Ghiti, Alexandre NoCArc '14: International Workshop on Network on Chip Architectures (2014) Cambridge United Kingdom 10.1145/2685342.2685344 Cited by (40) \| Cite \| Source