Michael A. Guillorn

ScholarGPS® ID: 31651165923103

Affiliation
International Business Machines Corporation, Armonk, New York, United States
Affiliation History

Field
Engineering and Computer Science
Discipline
Electrical and Computer Engineering
Top Specialties
Nanowire | Carbon Nanofiber | Nanofiber | Lithography | Semiconductor | CMOS | Nanotube | Carbon Nanotube | Metal Gate | Microelectronics | Dielectric | Nanostructure | Semiconductor Device | Field Electron Emission | Laser
Metrics Summary
Publication Count
370
Predicted Citations
8,862
Predicted h-index
56
Ranking

Publications and Citation History

Publications based on Top Specialties

Types of Publication

  • Publications
  • Books
  • Patents
  • NIH/NSF
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Nanosheet and nanowire MOSFET with sharp source/drain junction (patent)
Chang, Josephine B. | Cheng, Kangguo | Guillorn, Michael A. | Miao, Xin
Patent Number: 10840381 (2020)
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High density programmable e-fuse co-integrated with vertical FETs (patent)
Balakrishnan, Karthik | Guillorn, Michael A. | Hashemi, Pouya | Reznicek, Alexander
Patent Number: 10804278 (2020)
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Dielectric isolation and SiGe channel formation for integration in CMOS nanosheet channel devices (patent)
Guillorn, Michael A. | Loubet, Nicolas
Patent Number: 10741641 (2020)
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Generative adversarial networks for generating physical design layout patterns of integrated multi-layers (patent)
Sha, Jing | Guillorn, Michael A. | Burkhardt, Martin | Dunn, Derren N.
Patent Number: 10706200 (2020)
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Techniques for creating a local interconnect using a SOI wafer (patent)
Chang, Josephine B. | Guillorn, Michael A. | Lauer, Isaac | Sleight, Jeffrey W.
Patent Number: 10699955 (2020)
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Generative adversarial networks for generating physical design layout patterns (patent)
Sha, Jing | Guillorn, Michael A. | Burkhardt, Martin | Dunn, Derren N.
Patent Number: 10699055 (2020)
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Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs (patent)
Chang, Josephine B. | Guillorn, Michael A. | Lauer, Isaac | Miao, Xin
Patent Number: 10680061 (2020)
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Nanowire with sacrificial top wire (patent)
Chang, Josephine B. | Doris, Bruce B. | Guillorn, Michael A. | Lauer, Isaac | Miao, Xin
Patent Number: 10658461 (2020)
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Electrical mask validation (patent)
Corliss, Daniel | Dunn, Derren N. | Guillorn, Michael A. | Fetterolf, Shawn P.
Patent Number: 10650111 (2020)
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Classification and localization of hotspots in integrated physical design layouts (patent)
Sha, Jing | Shao, Dongbing | Burkhardt, Martin | Guillorn, Michael A.
Patent Number: 10621302 (2020)
Cited by (1) | Cite | Source
Coordinates-based variational autoencoder for generating synthetic via layout patterns (patent)
Sha, Jing | Guillorn, Michael A. | Dunn, Derren N.
Patent Number: 10621301 (2020)
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Semiconductor device including wrap around contact and method of forming the semiconductor device (patent)
Guillorn, Michael A. | Loubet, Nicolas Jean
Patent Number: 10615281 (2020)
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Method and recording medium of reducing chemoepitaxy directed self-assembled defects (patent)
Guillorn, Michael A. | Lai, Kafai | Liu, Chi-Chun | Raghunathan, Ananthan | Tsai, Hsinyu
Patent Number: 10606980 (2020)
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Coordinates-based generative adversarial networks for generating synthetic physical design layout patterns (patent)
Sha, Jing | Guillorn, Michael A. | Dunn, Derren N.
Patent Number: 10606975 (2020)
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Chemoepitaxy etch trim using a self aligned hard mask for metal line to via (patent)
Brink, Markus | Guillorn, Michael A. | Lin, Chung-Hsun | Tsai, HsinYu
Patent Number: 10600680 (2020)
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Automatic generation of via patterns with coordinate-based recurrent neural network (RNN) (patent)
Sha, Jing | Guillorn, Michael A. | Dunn, Derren N.
Patent Number: 10599807 (2020)
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Generating synthetic layout patterns by feedforward neural network based variational autoencoders (patent)
Sha, Jing | Guillorn, Michael A. | Dunn, Derren N.
Patent Number: 10592635 (2020)
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Gate-all-around field effect transistor having multiple threshold voltages (patent)
Bao, Ruqiang | Guillorn, Michael A. | Hook, Terence | Robison, Robert R. | Vega, Reinaldo | Yamashita, Tenko
Patent Number: 10586854 (2020)
Cited by (1) | Cite | Source
Preventing threshold voltage variability in stacked nanosheets (patent)
Guillorn, Michael A. | Loubet, Nicolas J.
Patent Number: 10580858 (2020)
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Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs (patent)
Chang, Josephine B. | Guillorn, Michael A. | Lauer, Isaac | Miao, Xin
Patent Number: 10573714 (2020)
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